Intel is integrating advanced "super-core processors" into their systems
In the fall of 2024, the x86 Ecosystem Advisory Group (EAG) was formed, a collaborative effort between tech giants AMD and Intel. This partnership marks a significant step forward in the development of the x86 architecture.
One of the most anticipated advancements from Intel is the upcoming release of the Nova Lake CPU, expected to hit LGA1954 boards by the end of 2026. This chip could be a game-changer, as it may be the first Intel CPU to incorporate APX and AVX10.2, promising enhanced computing capabilities.
Intel's Nova Lake CPU is built with a mix of efficiency cores (E-cores) and performance cores (P-cores). The E-cores are designed to be more compact than their P-counterparts, consuming less power and occupying less silicon area. However, they offer lower single-thread performance. In contrast, the P-cores deliver superior single-thread performance but consume more power and require more silicon area.
The size ratio of Intel's P-cores to E-cores is almost four to one, indicating a focus on balanced resource allocation.
A more general concept that Intel and AMD are exploring is the Coarse-Grain Reconfigurable Array (CGRA), which connects a certain number of small execution units depending on the computing task at hand. This design aims to provide the highest single-thread performance by offering as many parallel usable execution units as possible.
Intel has filed a patent for "Software-defined Supercores" (SDC), a concept that involves multiple slim CPU cores cooperating as needed to boost single-thread performance. The SDC operates with flow-control commands in the code, which provide hints about which code sections should be processed in parallel as much as possible.
AMD, on the other hand, is focusing on its Zen cores, with the Zen 5/5c architecture featuring more compact and efficient cores instead of E-cores. AMD Vice President Robert Hormuth announced FRED, AVX10, and APX as part of the EAG's agreements, but specific details about the planned innovations of the x86 architecture for fall 2024 remain elusive.
AVX10 and the Advanced Performance Extensions (APX) reorganize the AVX versions and bring twice as many registers, promising improved performance for complex mathematical operations.
It's worth noting that in the AMD Bulldozer architecture, two cores share certain execution units, such as the "Shared FPU". This design philosophy reflects a focus on efficient resource allocation and power management.
The aim of the SDC is to address the dilemma for CPU developers: To achieve the highest single-thread performance, a CPU core needs as many parallel usable execution units as possible. However, this often comes at the cost of increased power consumption and silicon area. The SDC seeks to strike a balance between these factors.
As the x86 Ecosystem Advisory Group continues to evolve, these advancements promise a future of more efficient, powerful, and versatile CPUs. Stay tuned for further developments in this exciting field.
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