Scientists successfully construct a 120-layer 3D DRAM structure using advanced deposition methods, bringing next-generation memory technology one step closer to reality.
In a significant leap forward for the electronics industry, researchers at imec and Ghent University have made a groundbreaking discovery that could revolutionize the design of chips. By growing 120 alternating layers of silicon (Si) and silicon-germanium (SiGe) on a 300 mm wafer, they have taken a key step towards three-dimensional DRAM.
This research aligns with ongoing efforts to develop Complementary FET (CFET) technologies, as well as Gate-All-Around Field-Effect Transistor (GAAFET) technologies. The goal is to improve storage capacity in DRAM without making chips larger, by stacking layers vertically instead of laying them out flat.
Each bilayer in the stack can be thought of as a story in a skyscraper, where misalignment of one floor can destabilize the entire building. To ensure stability, the researchers carefully tuned the germanium content in the SiGe layers and added carbon, which acts as a stress reliever.
Controlling layer properties at the atomic level is critical for quantum computing architectures, among other advanced technologies. Advanced epitaxial deposition techniques were used to grow the layers, where silane and germane gases were broken down on the wafer surface to create precise, nanometer-thin layers.
By controlling strain and keeping layers uniform, the researchers effectively built a nanoscale skyscraper of silicon and SiGe that could host thousands of memory cells per unit area. Successfully creating 120 bilayers demonstrates that vertical scaling is achievable, bringing us closer to next-generation, high-density memory devices.
However, it's important to note that the specific researchers working on 3D-DRAM development by reducing lattice mismatch and using carbon as a light adhesive are not identified in the provided search results.
The implications of this research extend beyond memory chips, potentially advancing 3D transistors, stacked logic devices, and quantum computing architectures. Controlling the thickness, composition, and uniformity of each layer is crucial to prevent defects from propagating through the stack.
Samsung, with its dedicated R&D facility for 3D DRAM, has 3D DRAM on its roadmap. The successful development of this technology could lead to denser, faster, and more reliable chips, reshaping the electronics industry as we know it. This research is not just stacking silicon; it's engineering order from atomic tension, creating structures that nature itself would struggle to produce.
